1. Field of the Invention
The present invention relates to a semiconductor device having the function of executing a reset operation of a word line connected to a specific memory cell, by driving the word line, in order to return the specific memory cell, in a memory cell array of a semiconductor memory, from an activated state to a standby state.
Demands for lower power consumption have been increasing in recent years in semiconductor devices comprising a semiconductor memory such as a dynamic random access memory (hereinafter abbreviated to “DRAM”) in consideration of battery driving. Therefore, power that is consumed in a circuit for executing the reset operation described above must be reduced as much as possible, too.
The present invention also relates to a semiconductor device for storing data by storing charges in memory cells and more specifically, to a semiconductor device which sets a word line potential at the time of non-selection to a negative potential so as to insure a safe and reliable operation even when a power source voltage is lowered so as to cope with higher circuit integration and even when a transistor threshold voltage value becomes low.
The present invention also relates to a semiconductor device including a plurality of power source circuits for generating different potentials by driving a capacitor by an oscillation signal, such as a step-up circuit (i.e., booster circuit) and a step-down circuit and more specifically, to a semiconductor device comprising a DRAM having such power source circuits.
2. Description of the Related Art
Generally, each of a plurality of memory cells that constitute a memory cell array in the DRAM includes one cell transistor for reading or writing data and one cell capacitor connected to the source of this cell transistor. The cell capacitor stores a charge depending on the logic “1” or “0” of the data written into the memory cell. A word line is connected to the gate of each cell transistor so as to supply a voltage necessary for bringing this cell transistor into an operating state (activated state).
When an N-channel transistor is used as the cell transistor inside each memory cell, a threshold voltage between the gate and the source of this N-channel transistor must be taken into consideration. In other words, when data is written or read by selecting a specific memory cell among a plurality of memory cells, a step-up voltage which is elevated by at least the threshold voltage between the gate and the source of the N-channel transistor is supplied from a word line to the gate of the N-channel transistor in order to reliably bring the cell transistor in this specific memory cell from the standby state to the activated state. Furthermore, in order to accomplish a high-speed operation of the DRAM, the cell transistor in the selected memory cell must be quickly returned from the activated state to the standby state after the data is written into, or read out, from the selected memory cell.
The operation that supplies a reset signal of a predetermined level from the word line to the cell transistor so as to return the cell transistor under the activated state to the standby state is generally referred to as the “reset operation” of the word line. A technology which sets the level of the reset signal (reset level, that is, reset potential) outputted from a word line driver circuit, to a potential of a negative voltage level (negative potential), but not to the ground potential, has been employed for this reset operation so as to minimize the leakage of the charges that are stored in the cell capacitor.
On the other hand, the integration density has become higher and higher in semiconductor memories (semiconductor memory devices) and scaling-down of the memory cell size has been made with a higher integration density. When the memory cell is scaled-down, a driving voltage must be lowered because the withstand voltage of the memory cell becomes low, and it becomes more difficult to insure a safe and reliable operation of the memory. Particularly in the case of the memories of such a type in which a capacitor is provided to each memory cell and the charge storing state and the charge non-storing state in the capacitor are allowed to correspond to the data values, as typified by the DRAM, the charges that are stored in the capacitor gradually drop due to the leakage current of the memory cell, and a re-write operation referred to as “refresh” must be carried periodically. When the memory cell is scaled down, the withstand voltage of the capacitor becomes low, so that a high voltage cannot be applied to the memory cell. In other words, the voltage of the power source must be lowered. The threshold voltage of the transistor must be also lowered with the decrease of the power source voltage, thereby inviting the problem that the leakage current when the cell transistor is not selected (sub-threshold leak) increases and the data retaining time becomes short. When the data retaining time becomes short, the cycle of the refresh operation must be shortened so as to cope with this short time, thereby inviting also the drop of performance of the DRAM such as the increase of the refresh current.
On the other hand, attempts have been made in recent years to reduce operating voltages of the semiconductor devices to improve the operation speed, to save power and to reduce noise. For instance, a driving voltage of 5 V has long been used for the semiconductor devices but recently, a 3.3 V voltage has been used and this voltage may become lower in the future. Nonetheless, such a voltage alone is not sufficient to insure stability of the operation, and a higher voltage and a negative voltage become necessary. Therefore, a step-up power source circuit (i.e., boosting power source circuit) and a step-down power source circuit are provided inside the semiconductor device so as to generate the necessary voltages in the semiconductor device. The DRAM, in particular, has been developed by simplifying as much as possible the construction so as to attain a high integration density but recently, a high operation speed has become also an important object in addition to the high integration density.
In order to make the problem that is encountered when the reset potential of the word line is set to the negative potential during the reset operation of the memory cell in the DRAM, more easily understood, the construction and operations of DRAMS, etc., according to the prior art that have the function of executing the reset operation will be explained with reference to FIGS. 1 to 5 of the accompanying drawings in the later-appearing “BRIEF DESCRIPTION OF THE DRAWINGS”.
FIG. 1 is a circuit diagram showing the construction of the first example of a semiconductor device having the function of setting a reset potential to a negative potential according to the prior art, and FIG. 2 is a timing chart useful for explaining the operation of the prior art device shown in FIG. 1. In this case, the drawings show the circuit construction for driving the word lines in the semiconductor device to simplify the explanation.
A word line driver 280 is shown disposed in FIG. 1 for supplying a driving signal SWL of a predetermined voltage level to the word line connected to the gate of the cell transistor inside the memory cell. This word line driver 280 includes an inverter comprising a P-channel transistor 285 and an N-channel transistor 290 for outputting the driving signal SWL on the basis of a selection signal, and an N-channel transistor 295 for clamping the word line at a predetermined reset level (reset potential) on the basis of a reset control signal SWDX. The source of each N-channel transistor 290, 295 is connected to a power source (negative power source) having a negative voltage Vnwl for resetting the word line. The N-channel transistor 295 becomes operative (ON) during the reset operation of the word line, and the output level of the driving signal SWL outputted from the word line driver circuit is substantially equal to the potential of the negative power source.
In FIG. 1, there is further disposed a word line driver control circuit 180 for controlling the voltage level of the driving signal SWL by supplying a high voltage side power source signal SWDZ to the P-channel transistor 285 of the word line driver 280. This word line driver control circuit 180 includes an inverter comprising a P-channel transistor 170 and an N-channel transistor 175. The source of the P-channel transistor 170 is connected to a power source of a step-up voltage Vpp, and the source of the N-channel transistor 175 is connected to the negative power source having a negative voltage Vnwl. Here, the high voltage side power source signal SWDZ of the step-up voltage Vpp or the negative voltage Vnwl is supplied to the high voltage side power source of the word line driver 280 on the basis of the control signal inputted from a node n01 on the input side of the inverter.
The operation of the semiconductor device of FIG. 1 is shown in the timing chart of FIG. 2. As is obvious from FIG. 2, when the memory cell is in a standby state, the signal level at the node n01, and the signal level at each portion, are as follows.
The signal level at the node n01=Vpp (high voltage level (“H (High)” level), the high voltage side power source signal SWDZ =Vnwl (low voltage level (“L (Low)” level), the selection signal MWL=Vpp, the reset controlling signal SWDX=Vii (“H” level). Therefore, the driving signal SWL=Vnwl. Here, symbol Vii represents the voltage of the step-down power source in the DRAM, and represents the “H” level which is lower than the “H” level of the step-up voltage Vpp.
Next, when the memory cell starts the active operation and enters the activated state, the memory cell is driven in such a manner that the level of the signal at the node n01 becomes equal to the negative voltage Vnwl and the level of the high voltage side power source voltage SWDZ reaches the step-up voltage Vpp. Further, the memory cell is controlled at the same timing so that the reset control signal SWDX becomes equal to Vnwl. Since the level of the selection signal MWL is set to the negative voltage Vnwl, the driving signal rises up to the step-up voltage Vpp.
The reset operation of the word line is executed when the activated state of the memory cell is returned to the standby state. In this case, the node n01 is first raised to the step-up voltage, so that the level of the high voltage side power source signal SWDZ reaches the voltage Vnwl. Since the level of the selection signal MWL remains the negative voltage Vnwl at this time, the P-channel transistor 285 becomes operative and the source of this transistor is connected to the node SWL. In consequence, the charges that are stored in the word line are absorbed by the negative power source through the P-channel transistor 285, and the potential of the node (word line) outputting the driving signal SWL drops. As the potential of this node lowers, the voltage comes close to the threshold voltage of the P-channel transistor 285. Therefore, a control is carried out at a suitable timing so that the selection signal MWL=Vpp. Furthermore, the node outputting the driving signal SWL is reset through the N-channel transistor 290 and is clamped at the negative voltage Vnwl. The negative voltage Vnwl clamped in this way corresponds to the reset potential of the word line.
In this case, all the charges Q (Q=(Vpp−Vnwl)×Cswl) charged to the node outputting the driving signal SWL must be absorbed by the negative power source having the negative voltage Vnwl. Here, symbol Cswl represents the total capacitance of the node.
The negative potential that is used for the reset operation of the word line and corresponds to the negative voltage Vnwl is not applied from outside the DRAM, and must be generated in the DRAM. A circuit that comprises an oscillating circuit unit and a pumping circuit unit is generally known as a negative potential generating circuit for generating such a negative potential.
Therefore, the construction of the semiconductor device according to the prior art, that absorbs the charge of the word line that is charged to the step-up voltage, under the activated state of the cell transistor, by the negative voltage, involves the problem that more power is consumed than in the construction in which the word line charge is absorbed by the power source of the ground potential. On the other hand, it is essentially necessary to set the potential at the time of the reset operation of the word line to a voltage level, which is as low as possible, in order to minimize the leak of the charge stored in the cell capacitor.
On the other hand, an increase in the refresh current causes a deterioration of a performance of the DRAM. To solve this disadvantage, Japanese Unexamined Patent Publication (Kokai) No. 9-134591 discloses a construction that reduces the sub-threshold leak by setting the potential of the non-selected word line (reset potential) to the negative potential below the ground level. FIG. 3 shows the basic construction of the semiconductor device as the second example of the prior art such as the device of Japanese Unexamined Patent Publication (Kokai) No. 9-134591. In addition to the conventional construction including the memory cell array, the word line driver (word line driver circuit) 200 and the X decoder (row decoder, that is, word line decoder) 300, a WL (word line) reset level generating circuit 400 is disposed so that the negative potential generated by this circuit 400 is supplied to the word line driver (word line driver circuit) 200.
The source and the drain of the cell transistor are connected to one of the ends of the capacitance and to the bit line, respectively. However, when the circuit is designed in such a manner that the potentials of the source and the drain do not fall to a level below the ground level, a negative bias voltage is applied between the gate and the source of the non-selected transistors if the potential of the word line connected to the gate of the cell transistor is lowered below the ground level. The larger becomes the negative value of the potential difference between the gate and the source of the transistor, the smaller becomes the sub-threshold leak of the transistor in a form of an exponential function, so that the decrease in the stored charges due to the leakage current can be reduced. Therefore, the reduction of the leakage current improves stability and reliability of the memory operation and accomplishes the improvement of performance such as the reduction of consumed power.
The negative potential generating circuit used in the second example of the conventional semiconductor devices allows the substrate potential of the cell transistor and its current supply/current absorption capability to be at a level that can sufficiently supplement the junction leak of the corresponding transistor. When the reset potential of the word line is set to the negative potential, however, a load such as the word line is charged and discharged by the negative potential power source. Therefore, a current supply capacity greater than that of the prior art devices becomes necessary. Japanese Unexamined Patent Publication (Kokai) No. 9-134591 discloses merely the disposition of the negative potential generating circuit but does not mention its construction, current supply capacity and current supplying method. However, it is assumed that the negative potential generating circuit that is disclosed in this reference quite naturally has a large current supply capacity.
When the negative potential generating circuit has a large current supply capacity, the power consumed in the negative potential generating circuit becomes great, too. Because the reduction of consumed power has been required for the semiconductor devices, the reduction of consumed power in the negative potential generating circuit is also required.
On the other hand, in order to cope with the disadvantage in which the operation of the semiconductor device becomes unstable due to lowering of the driving voltage, Japanese Unexamined Patent Publication (Kokai) No. 2-73593 discloses the construction for improving stability of the operation by increasing the voltage of the selected word line to a level higher than the voltage of the internal power source (internal voltage) and the power source voltage inputted from outside (external voltage). The aforementioned Japanese Unexamined Patent Publication (Kokai) No. 9-134591 discloses the construction for reducing the sub-threshold leak by setting the potential of the non-selected word lines (reset potential) to the negative potential below the ground level. Since the leak of the charges retained in the memory cell can be reduced in this way, the refresh cycle can be extended and consumed power can be reduced, as well.
FIG. 4 shows the voltage (potential) levels generated in the DRAM. The drawing shows the power source voltage levels generated on the chip with respect to the external power sources Vdd and GND, and these voltage levels are generated by the power source circuit that drives the capacitor by the oscillation signal. Symbol Vpp represents the “H” level of the selected word line, Vnwl represents the word line reset level, Vbb represents the back-bias voltage of the cell transistor and Vppr represents the step-up potential (i.e., step-up voltage) for generating Vg. Symbol Vg represents a constant potential used as the gate potential when the internally regulated voltage V2 is generated by using the N-channel transistor, as will be described later. Since Vg is V2+Vth (threshold voltage of the transistor), there is the case in which Vg>Vdd. Therefore, It is necessary to generate Vg from a potential higher than Vdd.
The negative potential Vbb is applied as the back-bias to the cell transistor so as (1) to prevent the forward-bias of the p-n junction inside the chip and to prevent also the destruction of the data and latch-up, (2) to reduce the change of the threshold voltage of the MOS transistor, (3) to reduce the junction capacitance by the back-bias (i.e., reverse-bias), and (4) to improve the transistor characteristics by increasing the threshold voltage of a parasitic MOS transistor.
The “H” level (Vpp) of the selected word line must be set to a level higher than “H” level of the cell stored charge+Vth.
Recently, the requirement for lowering the Vpp level has arisen with the progress of the lower voltage of the power source and lower power consumption of the semiconductor devices. To satisfy this requirement, the threshold voltage of the cell transistor must be lowered. When the threshold voltage of the cell transistor is lowered, however, the leakage current increases at the OFF time of the cell transistor and the holding time of the charge stored in the cell drops, so that the stable and reliable operation is impeded. To cope with the problem of lowering of the threshold voltage of the cell transistor, Japanese Unexamined Patent Publication (Kokai) No. 9-134591 proposes to set the word line reset level to the negative potential (Vnwl). If the word line reset level is kept at a potential lower than “L (Low)” of the bit line amplification, the negative bias is always applied between the gate and the source of the non-selected cell transistors in all the operating conditions, and the leakage current of the non-selected cell transistors can be thus reduced. In this way, a DRAM having high reliability can be accomplished.
As described above, various voltages are used in the DRAM other than the power source voltage supplied from external, and as to the power source voltage described above, power source circuits for generating different potentials by driving the capacitor with the oscillation signal are used.
FIG. 5 shows a structural example of the power source circuits in the conventional DRAM described above. As shown in the drawing, a plurality of power source circuits 10-0 to 10-n are provided on the chip. Each power source circuit includes an oscillation circuit 210 to 210-n, a capacitor drive circuit 230 to 230-n, a capacitor (pumping capacitor) 240 to 240-n and an output circuit (output transistor) 250 to 250-n, and outputs a voltage Vp1 to Vpn different from the external power source voltage.
The reduction of the chip area has been required for semiconductor devices so as to reduce the production cost. Also, the reduction of power consumption has been required to improve the chip performance (or chip characteristics). The semiconductor device includes a large number of power source circuits as shown in FIG. 5 in order to improve performance such as the high operation speed and the extension of the refresh time. From another aspect, however, this circuit construction invites the drop of performance such as the increase of the chip area and the increase of power consumption. It is therefore indispensable to reduce as much as possible a deterioration of performance in another aspect with the improvement of performance such as the high operation speed and the extension of the refresh time.